RISC-V Processor

RISC-V Processor


RISC-V combines a modular technical approach with an open, royalty-free ISA (Instruction Set Architecture). It leverages open-source solutions, offering flexibility, design freedom, and support for open architecture extensions to the RISC-V ISA.

Sailin develops cost-effective RISC-V SoCs (System on Chips) using its extensive IP portfolio, catering to a wide range of applications with 32-bit to 64-bit core chips:

1. Sailin Impala N Series MCU: Microcontroller chipsets for general-purpose applications.

2. Sailin Impala B Series MCU: Microcontroller chipsets designed for automotive electronics.

3. High-Performance Computing Processors: Next-generation 64-bit high-performance computing (HPC) processors.

The HPC (High-Performance Computing) processor deployed with RISC-V 64-bit ISA offers several advantages compared to the general CISC architecture. In RISC-V, a large number of registers are visible to the compiler, combined with a load/store architecture, and there are no memory-to-memory operations, resulting in fewer memory operations required. The use of the RISC-V weak memory ordering model, combined with fewer memory operations, enables dynamic execution optimization, which is not possible in the Total Store Order approach. This makes RISC-V processors excel in terms of Instructions Per Cycle (IPC) compared to some other deployments. Furthermore, optimized implementations of atomic memory operations, combined with cache hierarchy, improve the performance of multi-threaded applications, such as those running on large-scale HPC systems.

Sailin provides a comprehensive ecosystem, including IDEs, compilers, assemblers, linkers, debuggers, and tracing tools (supporting analysis and MC/DC security certification). All of these components have been carefully tested and integrated, delivering significant value to Sailin's strategic partners and customers.